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All | Freeware
Records 1-19
Product Title  /  Popularity Revised License Rating Size
Eclipse Verilog editor
Eclipse Verilog editor is a plugin for the Eclipse IDE. It provides Verilog(IEEE-1364) and VHDL language specific code viewer, contents outline, code assist etc. It helps coding and debugging in hardware development based on Verilog or VHDL.
November 27th 2012 Freeware    711k
Icarus Verilog
Icarus Verilog is an open source Verilog compiler that supports the IEEE-1364 Verilog HDL including IEEE1364-2005 plus extensions.
January 14th 2013 Freeware    1,184k
Mextram in Verilog-A
Verilog-A Implementation of the Mextram Bipolar Transistor Model
January 23rd 2013 Freeware    16k
PVSim Verilog Simulator
PVSim is a Verilog Simulator for Mac OS X that uses AlphaX editor's Verilog mode and features a fast compile-simulate-display cycle.
October 24th 2012 Freeware    1,584k
ED for Windows
ED for Windows is a smart language sensitive programmer&aposs editor, with a breadth and depth of powerful editing capabilities you&aposre unlikely to find elsewhere. ED goes beyond editing giving you instant access to every function and class with its Source ...
January 12th 2002 Commercial  5 stars 5k
Site Refiner
The main purpose of Site Refiner is to automatically find all files and page links in local site and bring them to the same specified case (usually to the lowercase). Site Refiner can do it fast and correct.
April 21st 2003 Shareware  4.5 stars 684k
Does what Spotlight does not. ScriptLight allows you to search and manage source code files on your computer. Do you use applescript? Do you dabble in shell scripting? Lots of us use languages to write things for our computers. Maybe ...
February 25th 2011 Shareware    2,693k
LogicSim is an affordable and user-friendly Verilog simulator for ASIC and FPGA design verification. It offers a powerful and easy-to-use graphical user interface that lets you quickly simulate your Verilog designs. It's built on our state-of-the-art single kernel simulation engine ...
May 8th 2011 Commercial    10,240k
CDL cycle language, compiler, simulator
Language, compiler and simulator for CDL cycle description language Platforms: OSX, Linux, Cygwin CDL is a C-like language for hardware description; simulator generates C++ models and synthesizable verilog. Includes C++ cycle simulation engine.
November 14th 2012 Freeware    464k
Doxverilog is a nativ Verilog/SystemVerilog parser for the Doxygen documentation generator. This allows the production of advanced documentation from Verilog/SystemVerilog sourcecode.
March 14th 2013 Freeware    221k
HDLObf is intended to be a HDL Obfuscator and identifier name change utility. Primarily designed for Verilog/SystemVerilog support will be added for VHDL/SystemC in future.
December 17th 2012 Freeware    143k
Icarus Verilog Interactive on MacOSX
January 26th 2013 Freeware    34,711k
A brand-new powerful major mode for editing verilog sources in Emacs.
January 16th 2013 Freeware    30k
GTKWave is a fully featured GTK+ based wave viewer for Unix, Win32, and Mac OSX which reads LXT, LXT2, VZT, FST, and GHW files as well as standard Verilog VCD/EVCD files and allows their viewing.
January 25th 2013 Freeware    12,800k
CoreTML Framework
CoreTML framework is an open-source template-based configuration system (template engine). It allows the developer to create parametrized templates by inserting special content to any text files. These templates can later be used to generate output files depending upon parameters chosen ...
June 23rd 2013 Freeware    1,741k
Simple Solver Logic
Simple Solver is a free Windows application that can simplify computer logic systems, Boolean equations, and truth tables. The application includes six different tools:Logic Design Draw, Logic Simulation, Logic Design Auto, Boolean, Permutation and Random Number. These tools are built ...
March 13th 2013 Freeware    1,536k
Qucs is a circuit simulator with graphical user interface. The software aims to support all kinds of circuit simulation types, e.g. DC, AC, S-parameter, Harmonic Balance analysis, noise analysis, etc. Until now there is no or little user documentation available. ...
March 10th 2013 Freeware    6,144k
Qfsm is a graphical editor for finite state machines written in C++ using Qt the graphical Toolkit from Trolltech. Finite state machines are a model to describe complex objects or systems in terms of the states they ...
February 13th 2013 Freeware    1,536k
Gorgeous Karnaugh Free
Gorgeous Karnaugh software: 1) Removes slow, tedious and error prone pen and paper from your life; 2) Gives you a pretty good logic simplification tool; 3) Supports definition of logic function using truth table, from analytic form or by direct ...
January 31st 2013 Freeware    1,761k
Related Scripts
Ruby interface to Verilog VPI
Ruby-VPI is a Ruby interface to IEEE 1364-2005 Verilog VPI. It lets you create complex Verilog test benches easily and wholly in Ruby.
March 9th 2012 Freeware     
VTracer is a Verilog Testbench developer aid. Contains well documented Verilog-Perl co-simulation environment (TCP sockets based), structural Verilog parser, demo Testbenches.
April 3rd 2012 Freeware     
Verilog / VHDL - little vs big Endian
Verilog / VHDL script allows you to easily to change all big-endian wires to big-endian in a Verilog file. This script was written for an x86 machine where there are only 8, 16, 32 bit registers. If you have a ...
March 4th 2012 Freeware     
Fixed-Point ATAN2 using CORDIC
This demo consists of a m-file script (fixed_point_atan2_using_cordic.m) and a m-file function (atan2_fixpt.m). The script contains a step-by-step explanation of how a four quadrant arctan can be calculated using a CORDIC (COordinate Rotation DIgital Computer) algorithm. The first part shows ...
June 8th 2013 Freeware    10k
Eclipse Verilog editor
Eclipse Verilog editor is a plugin for the Eclipse IDE. It provides Verilog(IEEE-1364) and VHDL language specific code viewer, contents outline, code assist etc. It helps coding and debugging in hardware development based on Verilog or VHDL.
March 27th 2013 Freeware    686k
Inferno C++ to Verilog
Convert C++ software programs into synthesisable Verilog using the Clang compiler frontend to parse and SystemC for intermediates.
March 5th 2013 Freeware     
Formal Checkers
Formal Checkers is an application development tool which helps you in creating simulation monitors, coverage analysis in order to track the occurrence of events of interest during the simulation. These checkers are used to monitor the simulation results on a ...
December 3rd 2005 Freeware     
Notepad is a free source code editor and Notepad replacement, which supports several programming languages, running under the MS Windows environment. This project, based on the Scintilla edit component (a very powerful editor component), written in C with pure win32 ...
January 6th 2012 Freeware     
DParser is an simple but powerful tool for parsing. You can specify the form of the text to be parsed using a combination of regular expressions and grammar productions. Because of the parsing technique (technically a scannerless GLR parser based ...
January 14th 2012 Freeware     
Sigma-Delta ADC, From Behavioral Model to Verilog and VHDL
For a full description of the models, refer to the September 2007 MATLAB Digest article. present a series of Simulink models to design a high-level behavioral model of a Sigma-Delta ADC. The high-level behavioral model has an Analog section and ...
April 26th 2013 Freeware    481k
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